[PATCH] avr/wdt: Fix support for atxmega devices

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[PATCH] avr/wdt: Fix support for atxmega devices

Ricardo Ribalda Delgado
On Xmega PER is located at bit 2, not at bit 0. Also the first timeout
is 8ms not 16, which means that me must add one to original PER value.

Checkout
page122
http://www.atmel.com/Images/doc8077.pdf
page 129
http://www.atmel.com/images/Atmel-42005-8-and-16-bit-AVR-Microcontrollers-XMEGA-E_Manual.pdf
page 127
http://www.atmel.com/Images/Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual.pdf

Signed-off-by: Ricardo Ribalda Delgado <[hidden email]>
---
 include/avr/wdt.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/avr/wdt.h b/include/avr/wdt.h
index a0a9f5ff7fd0..518a33725e27 100644
--- a/include/avr/wdt.h
+++ b/include/avr/wdt.h
@@ -166,7 +166,7 @@ __asm__ __volatile__ (         \
       [ccp_reg]            "I" (_SFR_IO_ADDR(CCP)),        \
       [ioreg_cen_mask]     "r" ((uint8_t)CCP_IOREG_gc),     \
       [wdt_reg]            "n" (_SFR_MEM_ADDR(WDT_CTRL)),   \
-      [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \
+      [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | ((timeout + 1) << 2))), \
       [wdt_status_reg]     "n" (_SFR_MEM_ADDR(WDT_STATUS)), \
       [wdt_syncbusy_bit]   "I" (WDT_SYNCBUSY_bm)            \
     : "r0" \
@@ -508,6 +508,10 @@ void wdt_disable (void)
    wdt_enable(WDTO_500MS);
    \endcode
 */
+#if defined(__DOXYGEN__) || defined(__AVR_XMEGA__)
+#define WDTO_8MS   -1
+#endif
+
 #define WDTO_15MS   0
 
 /** \ingroup avr_watchdog
@@ -538,7 +542,7 @@ void wdt_disable (void)
     See \c WDTO_15MS */
 #define WDTO_2S     7
 
-#if defined(__DOXYGEN__) || defined(WDP3)
+#if defined(__DOXYGEN__) || defined(WDP3) || defined(__AVR_XMEGA__)
 
 /** \ingroup avr_watchdog
     See \c WDTO_15MS
--
2.11.0


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